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To browse Academia.edu and the wider internet faster and more securely, please take a few seconds to upgrade your browser. Help Center less You can download the paper by clicking the button above. Related Papers Download pdf About Press Blog People Papers Job Board Advertise We're Hiring. First, there are additional instructions added to coordinate between threads. Second, there is contention for memory access. The way that the problem is stated, none of the code is inherently serial. All of it is parallelizable, but with scheduling overhead. One could argue that the memory access conflict means that to some extent memory reference instructions are not parallelizable. But based on the information given, it is not clear how to quantify this effect in Amdahl's equation. Data processing: The processor may perform some arithmetic or logic operation on data. Control: An instruction may specify that the sequence of execution be altered. Instruction address calculation (iac): Determine the address of the next instruction to be executed. Instruction fetch (if): Read instruction from its memory location into the processor. Instruction operation decoding (iod): Analyze instruction to determine type of operation to be performed and operand(s) to be used. Memory to processor: The processor reads an instruction or a unit of data from memory. Processor to memory: The processor writes a unit of data to memory. With multiple buses, there are fewer devices per bus. This (1) reduces propagation delay, because each bus can be shorter, and (2) reduces bottleneck effects. System pins: Include the clock and reset pins. Address and data pins: Include 32 lines that are time multiplexed for addresses and data. Interface control pins: Control the timing of transactions and provide coordination among initiators and targets. Arbitration pins: Unlike the other PCI signal lines, these are not shared lines.
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Rather, each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter. Thus, the data transfer rates differ by a factor of 1.5. The whole point of the clock is to define event times on the bus; therefore, we wish for a bus arbitration operation to be made each clock cycle. This requires that the priority signal propagate the length of the daisy chain (Figure 3.26) in one clock period. Thus, the maximum number of masters is determined by dividing the amount of time it takes a bus master to pass through the bus priority by the clock period. The lowest-priority device is assigned priority 16. This device must defer to all the others. However, it may transmit in any slot not reserved by the other SBI devices. At the beginning of any slot, if none of the TR lines is asserted, only the priority 16 device may transmit. This gives it the lowest average wait time under most circumstances. The length of the memory read cycle is 300 ns. b. The Read signal begins to fall at 75 ns from the beginning of the third clock cycle (middle of the second half of T,). Thus, memory must place the data on the bus no later than 55 ns from the beginning of T. The clock period is 125 ns. Therefore, two clock cycles need to be inserted. From Figure 3.19, the Read signal begins to rise early in T. To insert two clock cycles, the Ready line can be put in low at the beginning of T, and kept low for 250 ns. oP a. A5 MHz clock corresponds to a clock period of 200 ns. The instruction requires four memory accesses, resulting in 8 wait states. The instruction, with wait states, takes 24 clock cycles, for an increase of 50. b. In this case, the instruction takes 26 bus cycles without wait states and 34 bus cycles with wait states, for an increase of 33. a. The clock period is 125 ns. If both operands are even- aligned, it takes 2 us to fetch the two operands. If one is odd-aligned, the time required is 3 us. If both are odd-aligned, the time required is 4 us.
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-17- 3.17 Consider a mix of 100 instructions and operands. On average, they consist of 20 32- bit items, 40 16-bit items, and 40 bytes. For the 32-bit microprocessor, the number required is 100. Access must be made in a specific linear sequence. Direct access: Individual blocks or records have a unique address based on physical location. Access is accomplished by direct access to reach a general vicinity plus sequential searching, counting, or waiting to reach the final location. Random access: Each addressable location in memory has a unique, physically wired-in addressing mechanism. The time to access a given location is independent of the sequence of prior accesses and is constant. Faster access time, greater cost per bit; greater capacity, smaller cost per bit; greater capacity, slower access time. Itis possible to organize data across a memory hierarchy such that the percentage of accesses to each successively lower level is substantially less than that of the level above. Because memory references tend to cluster, the data in the higher- level memory need not change very often to satisfy memory access requests. Ina cache system, direct mapping maps each block of main memory into only one possible cache line. Associative mapping permits each main memory block to be loaded into any line of the cache. In set-associative mapping, the cache is divided into a number of sets of cache lines; each main memory block can be mapped into any line ina particular set. One field identifies a unique word or byte within a block of main memory. The remaining two fields specify one of the blocks of main memory. These two fields are a line field, which identifies one of the lines of the cache, and a tag field, which identifies one of the blocks that can fit into that line. A tag field uniquely identifies a block of main memory. A word field identifies a unique word or byte within a block of main memory.
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These two fields are a set field, which identifies one of the sets of the cache, and a tag field, which identifies one of the blocks that can fit into that set. Spatial locality refers to the tendency of execution to involve a number of memory locations that are clustered. Each set in the cache includes 3 LRU bits and four lines. Then, the required line is read into the cache. SRAM is used for cache memory (both on and off chip), and DRAM is used for main memory. SRAMs generally have faster access times than DRAMs. DRAMS are less expensive and smaller than SRAMs. A DRAM cell is essentially an analog device using a capacitor; the capacitor can store any charge value within a range; a threshold value determines whether the charge is interpreted as 1 or 0. A SRAM eell is a digital device, in which binary values are stored using traditional flip-flop logic-gate configurations. Microprogrammed control unit memory; library subroutines for frequently wanted functions; system programs; function tables. EPROM is read and written electrically; before a write operation, all the storage cells must be erased to the same initial state by exposure of the packaged chip to ultraviolet radiation. Erasure is performed by shining an intense ultraviolet light through a window that is designed into the memory chip. EEPROM isa read- mostly memory that can be written into at any time without erasing prior contents; only the byte or bytes addressed are updated. Flash memory is intermediate between EPROM and EEPROM in both cost and functionality. Like EEPROM, flash memory uses an electrical erasing technology. An entire flash memory can be erased in one or a few seconds, which is much faster than EPROM. In addition, it is possible to erase just blocks of memory rather than an entire chip. However, flash memory does not provide byte-level erasure. Like EPROM, flash memory uses only one transistor per bit, and so achieves the high density (compared with EEPROM) of EPROM. Als 1Mb 1Mb AO 5.5 a.
The length of a clock cycle is 100 ns. Mark the beginning of T, as time 0.Address Enable returns to a low at 75. RAS goes active 50 ns later, or time 125. Ability to support lower fly heights (described subsequently). Better stiffness to reduce disk dynamics. Greater ability to withstand shock and damage The write mechanism is based on the fact that electricity flowing through a coil produces a magnetic field. Pulses are sent to the write head, and magnetic patterns are recorded on the surface below, with different patterns for positive and negative currents. An electric current in the wire induces a magnetic field across the gap, which in turn magnetizes a small area of the recording medium. Reversing the direction of the current reverses the direction of the magnetization on the recording medium. The read head consists of a partially shielded magnetoresistive (MR) sensor. The MR material has an electrical resistance that depends on the direction of the magnetization of the medium moving under it. By passing a current through the MR sensor, resistance changes are detected as voltage signals. For the constant angular velocity (CAV) system, the number of bits per track is constant. An increase in density is achieved with multiple zoned recording, in which the surface is divided into a number of zones, with zones farther from the center containing more bits than zones closer to the center. Ona magnetic disk. data is organized on the platter in a concentric set of rings, called tracks. Data are transferred to and from the disk in sectors. For a disk with multiple platters, the set of all the tracks in the same relative position on the platter is referred to as a cylinder. 512 bytes. Ona movable-head system, the time it takes to position the head at the track is known as seek time. Once the track is selected, the disk controller waits until the appropriate sector rotates to line up with the head.
The time it takes for the beginning of the sector to reach the head is known as rotational delay. The sum of the seek time, if any, and the rotational delay equals the access time, which is the time it takes to get into position to read or write. The disk is divided into strips; these strips may be physical blocks, sectors, or some other unit. The strips are mapped round robin to consecutive array members. A set of logically consecutive strips that maps exactly one strip to each array member is referred to as a stripe. For RAID level 1, redundancy is achieved by having two identical copies of all data. For higher levels, redundancy is achieved by the use of error-correcting codes. Typically, the spindles of the individual drives are synchronized so that each disk head is in the same position on each disk at any given time. At a constant linear velocity (CLV), the disk rotates more slowly for accesses near the outer edge than for those near the center. Thus, the capacity of a track and the rotational delay both increase for positions nearer the outer edge of the disk. 1. Bits are packed more closely on a DVD. The spacing between loops of a spiral on a CD is 1.6 um and the minimum distance between pits along the spiral is 0.834 um. The DVD uses a laser with shorter wavelength and achieves a loop spacing of 0.74 um and a minimum distance between pits of 0.4 um. The result of these two improvements is about a seven-fold increase in capacity, to about 4.7 GB. 2. The DVD employs a second layer of pits and lands on top of the first layer A dual-layer DVD has a semireflective layer on top of the reflective layer, and by adjusting focus, the lasers in DVD drives can read each layer separately. However, because the entire track is buffered, sectors can be written back ina different sequence from the read sequence. Machine readable: Suitable for communicating with equipment.
Communication: Suitable for communicating with remote devices The most commonly used text code is the International Reference Alphabet (IRA), in which each character is represented by a unique 7-bit binary code; thus, 128 different characters can be represented. Control and timing. Processor communication. Device communication. The processor sends a request for the transfer of a block of data to the DMA module and is interrupted only after the entire block has been transferred. The full range of addresses may be available for both. Four general categories of techniques are in common use: multiple interrupt lines; software poll; daisy chain (hardware poll, vectored); bus arbitration (vectored). Typically, this would allow 128 devices to be addressed. However, an opcode specifies either an input or output operation, so it is possible to reuse the addresses, so that there are 256 input port addresses and 256 output port addresses. Because each device requires one command and one status port, the total number of ports is seven. c. seven. The printing rate is slowed to5 cps. The situation must be treated differently with input devices such as the keyboard. It is necessary to scan the buffer at a rate of at least once per 60 ms. Otherwise, there is the risk of overwriting characters in the buffer. If the device is ready, one output-type instruction is needed to present data to the device handler. The first time the alarm goes off, it alerts both that it is time to work on apples. The next alarm signal causes apple-server to pick up an apple an throw it over the fence. The third alarm is a signal to Apple-eater that he can pick up and eat the apple. The transfer of apples is in strict synchronization with the alarm clock, which should be set to exactly match Apple-eater's needs. This procedure is analogous to standard synchronous transfer of data between a device and a computer. On the third clock signal, the CPU reads the data.
If he must eat at a slower or faster rate than the clock rate, he will either have too many apples or too few. b. The women agree that A pple-server will pick and throw over an apple whenever he sees Apple-eater's flag waving. One problem with this approach is that if Apple-eater leaves his flag up, Apple-server will see it all the time and will inundate her friend with apples. This problem can be avoided by giving Apple-server a flag and providing for the following sequence: Apple-eater raises her \u201chungry\u201d flag when ready for an apple. Apple-server sees the flag and tosses over an apple. Apple-eater keeps her \u201chungry\u201d flag stays down until she needs another apple. One solution is to not permit apple-server to do anything but look for her friend's flag. This is a polling, or wait-loop, approach, which is clearly inefficient.. Assume that the string that goes over the fence and is tied to Apple-server's wrist. Apple-eater can pull the string when she needs an apple. When Apple- server feels a tug on the string, she stops what she is doing and throws over an apple. The string corresponds to an interrupt signal and allows Apple-server to use her time more efficiently. This occurs for two reasons: (1) a user page table can be paged in to memory only when it is needed. (2) The operating system can allocate user page tables dynamically, creating one only when the process is created. Of course, there is a disadvantage: address translation requires extra work. Twos Complement Representation: A positive integer is represented as in sign magnitude. A negative number is represented by taking the Boolean complement of each bit of the corresponding positive number, then adding 1 to the resulting bit pattern viewed as an unsigned integer. Biased representation: A fixed value, called the bias, is added to the integer. Insign-magnitude and twos complement, the left-most bit is a sign bit.
In biased representation, a number is negative if the value of the representation is less than the bias. Add additional bit positions to the left and fill in with the value of the original sign bit. Take the Boolean complement of each bit of the positive number, then adding 1 to the resulting bit pattern viewed as an unsigned integer. The twos complement representation of a number is the bit pattern used to represent an integer. The twos complement of a number is the operation that computes the negation of a number in twos complement representation. The algorithm for performing twos complement addition involves simply adding the two numbers in the same way as for ordinary addition for unsigned numbers, with a test for overflow. For multiplication, if we treat the bit patterns as unsigned numbers, their magnitude is different from the twos complement versions and so the magnitude of the result will be different. Sign, significand, exponent, base. An advantage of biased representation is that nonnegative floating-point numbers can be treated as integers for comparison purposes. Positive overflow refers to integer representations and refers to a number that is larger than can be represented in a given number of bits. Exponent overflow refers to floating point representations and refers to a positive exponent that exceeds the maximum possible exponent value. Significand overflow occurs when the -57- 9.11 9.12 9.13 9.1 9.2 9.3 addition of two significands of the same sign result ina carry out of the most significant bit. 1. Check for zeros. 2. Align the significands. 3. Add or subtract the significands. 4. Normalize the result. To avoid unnecessary loss of the least significant bit. Round to nearest: The result is rounded to the nearest representable number. Round toward \u2014 co: The result is rounded down toward negative infinity. Round toward 0: The result is rounded toward zero. If there is a carry out of the last magnitude bit, there is an overflow.
To represent the significands, 3 radix-10 digits are needed. The first shaded column contains the denormalized numbers. Registers and memory. Two operands, one result, and the address of the next instruction. Operation repertoire: How many and which operations to provide, and how complex operations should be. Data types: The various types of data upon which operations are performed. Instruction format: Instruction length (in bits), number of addresses, size of various fields, and so on. Registers: Number of CPU registers that can be referenced by instructions, and their use. Addressing: The mode or modes by which the address of an operand is specified. Addresses, numbers, characters, logical data. For the IRA bit pattern 011XXXxX, the digits 0 through 9 are represented by their binary equivalents, 0000 through 1001, in the right-most 4 bits. This is the same code as packed decimal. With a logical shift, the bits of a word are shifted left or right. On one end, the bit shifted out is lost. On the other end, a 0 is shifted in. The arithmetic shift operation treats the data as a signed integer and does not shift the sign bit. On a right arithmetic shift, the sign bit is replicated into the bit position to its right. On a left arithmetic shift, a logical left shift is performed on all bits but the sign bit, which is retained. 1. In the practical use of computers, it is essential to be able to execute each instruction more than once and perhaps many thousands of times. It may require thousands or perhaps millions of instructions to implement an application. This would be unthinkable if each instruction had to be written out separately. Ifa table ora list of items is to be processed, a program loop is needed. One sequence of instructions is executed repeatedly to process all the data. 2. Virtually all programs involve some decision making. We would like the computer to do one thing if one condition holds, and another thing if another condition holds. 3. To compose -69- b.
For addition, we again need a location, M(0), whose initial value is 0. We also need destination location, M(1). When it is desired to interrupt a program at a particular point, the NOOP is replaced with ajump to a debug routine. When temporarily patching or altering a program, instructions may be replaced with NOOPs. 2. A NOOP introduces known delay into a program, equal to the instruction cycle time for the NOOP. If the stack is also used to pass parameters, then the scheme will work only if it is the control unit that removes parameters, rather than machine instructions. In the latter case, the CPU would need both a parameter and the PC on top of the stack at the same time. 10.12 The DAA instruction can be used following an ADD instruction to enable using the add instruction on two 8-bit words that hold packed decimal digits. If there is a decimal carry (i.e., result greater than 9) in the rightmost digit, then it shows up either as the result digit being greater than 9, or by setting AF. If there is such a carry, then adding 6 corrects the result.Thus, the leftmost bit of a byte is bit 7 but has a bit offset of 0, and the rightmost bit of a byte is bit 0 but has a bit offset of 7. -79- 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 b. 2 times: fetch instruction; fetch operand reference and load into PC. Load the address into a register. Then use displacement addressing with a displacement of 0. The PC-relative mode is attractive because it allows for the use of a relatively small address field in the instruction format. For most instruction references, and many data references, the desired address will be within a reasonably short distance from the current PC address. This is an example) of a special-purpose CISC instruction, designed to simplify the compiler. Consider the case of indexing an array, where the elements of the array are 32 bytes long. No, because the second element of the stack is fetched twice.
Stack (top on left) PUSH 4 4 PUSH 7 7,4 PUSH 8 37,4 ADD 15,4 PUSH 10 10, 15,4 SUB 54 MUL 20 The 32-bit instruction length yields incremental improvements. The 16-bit length can already include the most useful operations and addressing modes. Thus, relatively speaking, we don't have twice as much \u201cutility\u201d. With a different word length, programs written for older IBM models would not execute on the newer models. Thus the huge investment in existing software was lost by converting to the newer model. Bad for existing IBM customers, and therefore bad for IBM. -82- 11.16 11.17 11.18 11.19 Let X be the number of one-address instructions. The scheme is similar to that for problem 11.16. Divide the 36-bit instruction into 4 fields: A, B, C, D. Field A is the first 3 bits; field B is the next 15 bits; field C is the next 15 bits, and field D is the last 3 bits. The 7 instructions with three operands use B, C, and D for operands and A for opcode. Let 000 through 110 be opcodes and 111 be a code indicating that there are less than three operands. The program has 12 instructions, 7 of which have an address. The program has 11 instructions. If the two opcodes conflict, the instruction is meaningless. If one opcode modifies the other or adds additional information, this can be viewed as a single -83- opcode with a bit length equal to that of the two opcode fields. Each value can be interpreted to ways, depending on whether the Operand 2 field is all zeros, for a total of 64 different opcodes. b. We could gain an additional 32 opcodes by assigning another Operand 2 pattern to that purpose. For example, the pattern 0001 could be used to specify more opcodes. The tradeoff is to limit programming flexibility, because now Operand 2 cannot specify register R1. This causes a delay in loading one of the streams.
The delay may be increased if a component of the address calculation is a value that is not yet available, such as a displacement value in a register that has not yet been stored in the register. Other delays relate to contention for the register file and main memory. (2) The cost of replicating significant parts of the pipeline is substantial, making this mechanism of questionable cost-effectiveness. 12.13 a. 12.14 a. Call the first state diagram Strategy A. Strategy A corresponds to the following behavior. If both of the last two branches of the given instruction have not taken the branch, then predict that the branch will not be taken; otherwise, predict that the branch will be taken. Call the second state diagram Strategy B. Strategy B corresponds to the following behavior. Two errors are required to change a prediction. That is, when the current prediction is Not Taken, and the last two branches were not taken, then two taken branches are required to change the prediction to Taken. Similarly, if the current prediction is Taken, and the last two branches were taken, then two not-taken branches are required to change the prediction to Not Taken. However, if there is a change in prediction followed by an error, the previous prediction is restored. Strategy A works best when it is usually the case that branches are taken. In both Figure 12.17 and Strategy B, two wrong guesses are required to change the prediction. Thus, for both a loop exit will not serve to change the prediction. When most branches are part of a loop, these two strategies are superior to Strategy A. The difference between Figure 12.17 and Strategy B is that in the case of Figure 12.17, two wrong are also required to return to the previous prediction, whereas in Strategy B, only one wrong guess is required to return to the previous prediction. It is unlikely that either strategy is superior to the other for most programs.
The comparison of memory addressed by AO and A1 renders the BNE condition false, because the data strings are the same. The program loops between the first two lines until the contents of D1 are decremented below 0 (to -1). At that point, the DBNE loop is terminated. The software approach is to rely on the compiler to maximize register usage. The compiler will attempt to allocate registers to those variables that will be used the most in a given time period. This approach requires the use of sophisticated program-analysis algorithms. The hardware approach is simply to use more registers so that more variables can be held in registers for longer periods of time. 13.3 (1) Variables declared as global in an HLL can be assigned memory locations by the compiler, and all machine instructions that reference these variables will use memory-reference operands. (2) Incorporate a set of global registers in the processor. These registers would be fixed in number and available to all procedures 13.4 One instruction per cycle. Register-to-register operations. Simple addressing modes. Each D phase adds delay, so that term still must be included. Finally, each jump wastes the next instruction fetch opportunity. However, as can be seen in Figure 13.6, the data fetch is not completed prior to the execution of the following instruction. If this following instruction utilizes the fetched data as one of its operands, it must wait one phase. Solution Manual Computer Organization And Architecture 8th Edition.pdf. TABLE OF CONTENTS ITrtroduction.essescssessssesecsseeseeesneessneeeenee Computer Evolution and Performance. Operating System Support. Computer Arithmetic. Instruction Sets: Characteristics and Functions Instruction Sets: Addressing Modes and Format: Processor Structure and Function. Reduced Instruction Set Computers. Instruction-Level Parallelism and Superscalar Processor: Control Unit Operation. Microprogrammed Contro Parallel Processing. Multicore Computers.
Number Systems Digital Logic. The instruction contains the address of the data we want to load. During the execute phase accesses memory to load the data value located at that address for a total of two trips to memory. 2.3 Toreada value from memory, the CPU puts the address of the value it wants into the MAR. The CPU then asserts the Read control line to memory and places the address on the address bus. Memory places the contents of the memory location passed on the data bus. This data is then transferred to the MBR. To write a value to memory, the CPU puts the address of the value it wants to write into the MAR. The CPU also places the data it wants to write into the MBR. The CPU then asserts the Write control line to memory and places the address on the address bus and the data on the data bus. When an address is presented to a memory 2.7 2.8 2.9 module, there is some time delay before the read or write operation can be performed. While this is happening, an address can be presented to the other module. For a series of requests for successive words, the maximum rate is doubled. The discrepancy can be explained by noting that other system components aside from clock speed make a big difference in overall system speed. A system is only as fast as its slowest link. In recent years, the bottlenecks have been the performance of memory modules and bus speed. As noted in the answer to Problem 2.7, even though the Intel machine may have a faster clock speed (2.4 GHz vs. 1.2 GHz), that does not necessarily mean the system will perform faster. Different systems are not comparable on clock speed. Other factors such as the system components (memory, buses, architecture) and the instruction sets must also be taken into account. A more accurate measure is to run both systems on a benchmark. Benchmark programs exist for certain tasks, such as running office applications, performing floating-point operations, graphics operations, and so on.